In the past few days, I attended the first Global RISC-V Open Workshop (GROW 2025), organized through a joint collaboration between the Universidade de São Paulo (USP), the Universidade Estadual de Campinas (Unicamp), and several universities and research centers in China. The event was hosted in São Paulo at the INOVA Center, located on the USP campus. The keynotes were very insightful, and I'd like to use this post to document the experience I had at this exciting event.
XiangShan and the OSOC Initiative #
On Monday morning, Professor Yungang Bao presented the work he and his team have been doing with RISC-V microprocessors. Two things stood out: the XiangShan processor and the One Student One Chip (OSOC) initiative.
XiangShan is an open-source, high-performance RISC-V processor, now in its third iteration, with impressive performance and silicon technology. The latest version, called Kunminghu, features a 14-stage pipeline and implements the RVA23 profile. It runs at 3 GHz and uses a 7nm process. Incredible.
The other highlight was the One Student One Chip initiative, which allows students to learn the entire chip design process at their own pace. If certain milestones are reached, the design actually goes to tape-out, and students can run Linux on the processor they designed themselves! This initiative isn't limited to Chinese students. We witnessed the first chip designed in Kazakhstan through OSOC. There were many educators at the event, and I noticed they were all eager to learn more and possibly bring the initiative to Brazil.
Compiler Optimization and RISC-V Matrix Extension #
On Tuesday, Professors Guido Araujo and Lucas Wanner from Unicamp presented some of the projects being developed at the Laboratory of Computer Systems (LSC) in collaboration with various companies. Guido discussed compiler optimizations for convolutions using MLIR, and Lucas presented a RISC-V matrix processor currently being designed at the Eldorado Institute. I happen to work on both of these projects, so it was exciting for me to see our work being showcased to a broader audience.
Caninos Loucos #
Professor Marcelo Zuffo from USP introduced us to the RISC-V chips developed at CITI (Interdisciplinary Center for Innovative Technologies). He emphasized the importance of having a fully open computing stack: from applications to operating systems, hardware, and even materials. His lab is called Caninos Loucos (which means "mad dogs" in English), a nod to John "maddog" Hall, who visited Brazil on several occasions and advocated for the country to design its own processors.
David Patterson #
The most anticipated presentation came from the legend himself, Professor David Patterson. Unfortunately, he couldn't attend in person, but he gave a virtual talk on the history and future of RISC-V. I was amazed to learn that RISC-V was originally created for teaching purposes only. However, it quickly gained traction worldwide and was eventually formalized as an open standard.
Patterson mentioned some extinct ISAs (e.g., Sun SPARC, DEC Alpha) and how Intel's x86 architecture may be in trouble moving forward, opening a path for RISC-V's success. Someone in the audience asked an insightful question: "If ISAs have died in the past, will RISC-V die one day too?" Patterson replied that ISAs typically die in one of two ways: either the company behind them goes out of business, or the ISA fails to evolve with new computing requirements (e.g., bus width). RISC-V is an open standard, so no single company controls it. It's also modular and extensible, capable of adapting to new requirements as they appear. Moreover, the RISC-V standard already specifies 128-bit processors, which may be enough for a really long time. From his perspective, RISC-V seems to have a bright future ahead.
Closing Thoughts #
All in all, I was very pleased to participate in this event. I was joined by colleagues from Unicamp and had the pleasure of meeting some friends in person at USP. It was both fun and inspiring. Now, I go back to work.